In order to increase memory capacity, manufacturers have continually moved memory chip or on-chip memory (such as flash memory) production to smaller process geometries over the last few years. Recently, multi-level signal memory cells have been used to increase flash memory capacity. In such an arrangement, a cell is configured to produce distinct signal threshold levels, which results in distinct read-back levels. With four level signals available per cell, two bits may be included into each flash memory cell. One problem with writing with four signal levels into each cell is that the distinction between adjacent levels may become difficult to discern. This is often referred to in the art as reduced signal distance (often shown as reduced Dmin).
When writing a signal level to a given cell, there is generally an amount of uncertainty in the written-in signal level. When the probable distribution of each signal level overlaps the probable distribution of adjacent signal level, the signal level generally may not be determined by using a simple prior art slicer circuit. This results in a limit on the number of signal levels that may be employed to write into every cell. At present, the state of the art is four signal levels, or two bits per cell.